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| CXB1583Q 266Mbaud Fibre Channel Transceiver IC For the availability of this product, please contact the sales office. Description The CXB1583Q is a transceiver IC with the built-in PLLs into a single chip. For receiver, the 265.625Mbaud serial data is received and it is output as a 10-bit parallel data; for transmitter, the 265.625Mbaud 10-bit parallel data is received and it is output as a serial data after conversion. Features * Transmitter/receiver into a single chip * Conforms to ANSI X3T11 fibre channel standard * PLL for a clock synthesizing and for clock recovery * Single 3.3V power supply * Low power consumption: 860mW (Typ.) * 80-pin plastic package * Comma signal detector * Test pattern (K28.5) generation circuit * Loop-back circuit * Supports data rage of 200Mbaud LCKREF 80 pin QFP (Plastic) Applications 265.625Mbaud fibre channel Structure Bipolar silicon monolithic IC TXSOUT TXSOUT Pin Configuration TJMON VEEP2 VEEP1 LPFD LPFC ECK SDIN REXT LPFB 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SDOUT 61 SDOUT 62 VCCE 63 VEEE 64 TXSIN 65 TXSIN 66 LOL 67 VEEG 68 VCCG 69 ECKENB 70 VEEG 71 VCCG 72 LPBK 73 ALTENB 74 TPGEN 75 TXSER 76 REFCLK 77 VEET 78 VCCG 79 VEEG 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 MS1 39 MS0 38 CDETENB 37 VCCT 36 POR 35 TXLKDT 34 RXLKDT 33 VEET 32 PCLKOUT0 31 PCLKOUT1 30 VEEG 29 VCCG 28 CDET 27 PDO9 26 PDO8 25 VEET 24 PDO7 23 VCCT 22 VCCG 21 VEEG ECK PDO0 PDO3 PDO4 PDI4 PDI3 PDI9 VCCT PDI2 PDI8 SDIN VEEG PDO5 PDO2 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- PDO1 PDO6 PDI1 PDI7 VEET PDI0 PDI6 VEET PDI5 VCCG LPFA VCCP VEEE VCCE E96501-ST CXB1583Q Absolute Maximum Ratings Item Power supply TTL DC input voltage ECL DC input voltage ECL differential input voltage TTL output current (high level) TTL output current (low level) ECL output current Operating ambient temperature Storage temperature Symbol VCC VI_T VI_E VIS_E IOH_T IOL_T IO_E Ta Tstg Min. -0.3 -0.5 VCC - 2 -2 -20 0 -30 -55 -65 (VEEE, VEET, VEEG, VEEP = 0V) Typ. Max. 4 5.5 VCC 2 0 20 0 70 150 Unit V V V V mA mA mA C C Recommended Operating Conditions Item Supply voltage Ambient temperature Symbol VCC Ta Min. 3.135 0 (VEEE, VEET, VEEG, VEEP = 0V) Typ. 3.3 Max. 3.465 70 Unit V C -2- CXB1583Q Block Diagram TPGEN TXSER TXSIN TXSIN TXSOUT TXSOUT 10 PDI (0 to 9) 26.6Mbps DQ 10 K28.5 Gen. 1 0 Pin P/S Sout 0 1 SDOUT SDOUT ALTENB TXCLK (26.6MHz) REFCLK REFCLK (26.6MHz) TXLOAD (266MHz) TX_PLL TXLKDT LPFA LPBK LPFB RTDATA REXT VEEP 10 PDO (0 to 9) 26.6Mbps S/P RXCLK (266MHz) RPCLK (26.6M) SDIN RX_PLL 1 0 SDIN LOL CDET RXLKDT PCLKOUT0 PCLKOUT1 CDETENB -3- LCKREF LPFC LPFD CXB1583Q Pin Description Pin No. Symbol Type Typical pin I/O voltage VCCG Equivalent circuit Description 1 to 10 PDI0 to 9 TTL input TTL level TTL-IN Parallel data input. VEET VEEG VCCT 11, 12, 14, 16, TTL 17, 19, PDO0 to 9 output 20, 24, 26, 27 TTL-OUT TTL level Parallel data output. VEET 13, 18, 25, 33, VEET 78 15, 23, VCCT 37 21, 30, 42, 68, VEEG 71, 80 22, 29, 41, 69, VCCG 72, 79 Power supply Power supply Power supply Power supply 0V -- Negative power supply for TTL input/output. Positive power supply for TTL output. Negative power supply for internal logic gate. Positive power supply for internal logic gate. VCCT 3.3V -- 0V -- 3.3V -- 28 CDET TTL output TTL-OUT TTL level Byte synchronization output. Outputs high level when +Comma (0011111) or -Comma (1100000) is detected to the serial data. VEET -4- CXB1583Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit VCCT Description 32 PCLKOUT0 TTL output TTL-OUT TTL level Receive byte clock 0 output. This clock is used to take the parallel data (PDO0 to 9) at the next-stage system. VEET VCCT 31 TTL PCLKOUT1 output TTL-OUT TTL level Receive byte clock 1 output. PCLKOUT0 inverted clock. VEET VCCT 34 RXLKDT TTL output TTL-OUT TTL level VEET RX_PLL lock detection signal output. Outputs high level when the PLL is locked to the serial data or the serial data has no signal; Outputs low level when the PLL is not locked. RXLKDT output may sporadically go high when the PLL starts to lock to the serial data. TX_PLL lock detection signal output. Outputs high level when the PLL is locked to REFCLK and operating normally; Outputs low level when the PLL is not operating normally. VCCT 35 TXLKDT TTL output TTL-OUT TTL level VEET -5- CXB1583Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit VCCT Description 36 POR TTL output TTL-OUT TTL level Power-on reset signal output. Outputs high level after the power is turned on and low level is held for approximately 100ns. VEET VCCG 38 CDETENB TTL input TTL level TTL-IN VEET VEEG Byte synchronization enable signal input. When high level is input, +Comma (0011111) or -Comma (1100000) is detected and the parallel data is synchronized with this byte. (See the Timing Chart.) When low level is input, byte synchronization is not performed. VCCG 39, 40 MS0, MS1 TTL input 3.3 V or TTL high level TTL-IN Test pin. Connect to Vcc. VEET VEEG VCCE VCCG 43, 44 SDIN SDIN ECL input (differential) ECL-IN ECL level ECL-IN VCCE - 1.3V Serial data input. VEEE VEEG 45, 63 46, 64 VCCE Power supply Power supply 3.3V -- Positive power supply for ECL input/output. Negative power supply for ECL input/output. VEEE 0V -6- -- CXB1583Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description VCCE 47, 48 ECL TXSOUT output TXSOUT (differential) ECL-OUT ECL level ECL-OUT Parallel/serial conversion output. This output is enabled when TXSER is high. VEEE VCCE VCCG 49, 50 ECK ECK One is left ECL open; another output is connected (differto Vcc via ential) 47k. ECL-IN VCCE - 1.3V ECL-IN Test pin. Connect either of these pins to Vcc via a 47k resistor. VEEE VEEG 51 VCCP Power supply 3.3V -- Positive power supply for internal PLL. VCCP 52, 53 LPFA LPFB External part connection LPF_C LPF_D -- RX_PLL external loop filter connection. (See Fig. 1 of the Notes on Operation.) VEEP1 VEEP2 54, 55 VEEP1 VEEP2 Power supply 0V -- VCCP Negative power supply for internal PLL. 56 REXT External part connection -- REXT Connects the resistor which determines the VCO center frequency. (See Fig. 1 of the Notes on Operation.) VEEP2 -7- CXB1583Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit VCCP Description 57 TJMON Test pin TJMON 0V Junction temperature measurement. VEEE2 VCCP 58, 59 LPFC LPFD External part connection LPF_C LPF_D -- TX_PLL external loop filter connection. (See Fig. 1 of the Notes on Operation.) VEEP2 VEEP1 VCCG 60 LCKREF TTL input TTL level TTL-IN Lock-to-reference signal input. When this pin is set to low level, RX_PLL is forcibly locked to REFCLK. VEEG VEET VCCE 61, 62 SDOUT SDOUT ECL output (differential) ECL-OUT ECL level ECL-OUT Serial data output for transmission. The serial data order is PDI0 PDI9. VEEE -8- CXB1583Q Pin No. Symbol Type Typical pin I/O voltage VCCE Equivalent circuit Description VCCG 65, 66 TXSIN TXSIN ECL input (differential) ECL-IN ECL level ECL-IN VCCE - 1.3V Serial ECL data input. When TXSER is high, this input signal is output from SDOUT. VEEE VEEG VCCE VCCG 67 LOL ECL input Open or ECL (single level phase) ECL-IN VCCE - 1.3V Lost-of-light signal input. Low level when this pin is left open. VEEE VEEG VCCG 70 ECKENB TTL input 3.3V or TTL high level TTL-IN Test pin. VEET VEEG VCCG 73 LPBK TTL input TTL level TTL-IN VEET VEEG Loop-back enable. If LPBK is set to high, the signal output from SDOUT when LPBK is low is transmitted to the RX input with the internal connection. In this time, SDOUT/ SDOUT are fixed to low/high respectively and SDIN/SDIN are both disabled. -9- CXB1583Q Pin No. Symbol Type Typical pin I/O voltage VCCG Equivalent circuit Description Alternate disparity test pattern generation enable. When ALTENB is set to low with TPGEN low, K28.5 (+K28.5, -K28.5) is generated for the data stream output. When this pin is high, +K28.5 is generated. 74 ALTENB TTL input TTL level TTL-IN VEET VEEG VCCG 75 TPGEN TTL input TTL level TTL-IN Test pattern generation enable. When this pin is low, +K28.5 (ALTENB: high) or K28.5 (ALTENB: low) is generated for the data stream output. VEEG VEET VCCG 76 TXSER TTL input TTL level TTL-IN VEET Transmit serial data selector. When this pin is high, the serial data input from TXSIN is output from SDOUT and the serialized PDI0 to 9 signals are output from TXSOUT. VEEG VCCG 77 REFCLK TTL input TTL level TTL-IN VEET VEEG Transmit byte clock. This clock is used to take the PDI0 to 9 signals in the TXPLL. The RXPLL takes the frequency from REFCLK when LCKREF is low. REFCLK is necessary after LCKREF is set to high and the RXPLL is locked to the serial data. - 10 - CXB1583Q CXB1583Q Functions 1. Data map to the 8b/10b alphabet notation PDI0 is the start bit. PDI, PDO 8b/10b alphabet notation 0 a 1 b 2 c 3 d 4 e 5 i 6 f 7 g 8 h 9 j 2. COMMA DETECT When CDETENB is high and the SDIN input data row includes K28.5, PDO0 to 9 are synchronized with K28.5 and output. Byte synchronization is also performed to Comma. Serial Data +K28.5 Comma (positive) Comma (negative) -K28.5 PDO0 a 0 0 1 1 b 0 0 1 1 c 1 1 0 0 d 1 1 0 0 e 1 1 0 0 i 1 1 0 0 f 1 1 0 0 g 0 X X 1 h 1 X X 0 PDO9 j 0 X X 1 3. TXSER, LPBK operation modes Input TXSER Low Low High High Low High Low High LPBK TXSOUT Disabled/Static Disabled/Static Serialized PDI Serialized PDI Output SDOUT Serialized PDI Disabled/Static TXSIN Disabled/Static PDO0 to 9 SDIN PDI SDIN TXSIN 4. LCKREF operation modes LCKREF input level High Low RXPLL comparison signal SDIN, SDIN REFCLK 5. CDETENB CDETENB input level High Low Operation Byte synchronization with the Comma signal Byte synchronization function stop - 11 - CXB1583Q Electrical Characteristics DC Characteristics (under the recommended operating conditions) Item TTL high level input voltage TTL low level input voltage TTL high level input current TTL low level input current Symbol VIH_T VIL_T IIH_T IIL_T -400 2.2 0.5 VCC - 1.17 VCC - 1.81 200 VCC - 1.05 VCC - 1.81 650 260 0.86 341 1.18 VCC - 0.88 VCC - 1.48 1000 VCC - 0.81 VCC - 1.55 Min. 2 0 Typ. Max. 5.5 0.8 20 Unit V V A A V V V V mV V V mV mA W AC coupling input 50 terminated to Vcc - 2 V 50 terminated to Vcc - 2 V 50 terminated to Vcc - 2 V Output pins open Output pins open VIH = VCC VIL = 0 IOH = -0.4mA IOL = 2mA Conditions TTL high level output voltage VOH_T TTL low level output voltage VOL_T ECL high level input voltage ECL low level input voltage VIH_E VIL_E ECL differential input voltage VIS_E ECL high level output voltage VOH_E ECL low level output voltage VOL_E ECL output amplitude Current consumption Power consumption VOS_E ICC PD - 12 - CXB1583Q AC Characteristics (under the recommended operating conditions) Item PDI rise time PDI fall time REFCLK rise time REFCLK fall time TTL output rise time TTL output fall time ECL output rise time ECL output fall time SDIN data rate REFCLK cycle tolerance REFCLK duty cycle PCLKOUT0 and 1 skew PDI setup time PDI hold time PDO setup time PDO hold time TX deterministic jitter (p-p) TX random jitter (p-p) RX jitter tolerance Symbol Tir_PDI Tif_PDI Tir_RFCK Tif_RFCK Tor_T Tof_T Tor_E Tof_E R_SDIN Ttol_RFCK DC_RFCK Tskew Ti_s Ti_h To_s To_h DJ RJ JT 190 -200 40 -3 4 3 10 12 0.08 0.15 0.7 0 0.375 0.375 Min. Typ. Max. 10 10 5 5 5 5 500 500 280 200 60 3 Unit ns ns ns ns ns ns ps ps Mbaud ppm % ns ns ns ns ns UI UI UI REFCLK reference REFCLK reference PCLKOUT0 reference PCLKOUT0 reference Serial data output Serial data output Serial data input SDIN cycle reference Conditions 0.8 to 2.0V 2.0 to 0.8V 0.8 to 2.0V 2.0 to 0.8V 0.8 to 2.0V, CL = 10pF 2.0 to 0.8V, CL = 10pF 20 to 80%, CL = 2pF 20 to 80%, CL = 2pF PLL AC Characteristics (under the recommended operating conditions) Item TX/PX PLL frequency acquisition time RX PLL bit synchronization time Symbol Tfa Tbs Min. Typ. Max. 500 2500 Unit s bit Conditions Loop damping capacitance = 0.01F - 13 - CXB1583Q Timing Chart for TX 2.0V 1.5V 0.8V Tir_RFCK Tif_RFCK REFCLK Ti_s Ti_h 2.0V VALID VALID 1.5V 0.8V Tir_PDI Tif_PDI PDI0 to 9 Timing Chart for RX 1.5V PCLKOUT1 Th_PCK Tl_PCK Tskew 2.2V 1.5V 0.6V Tor_PCK Tof_PCK PCLKOUT0 To_s To_h 2.2V VALID VALID 0.6V PDO0 to 9 Tor_PDO Tof_PDO - 14 - CXB1583Q Electrical Characteristics Measurement Circuit (See "Fig. 3 Power Supply Circuit" regarding the power supply.) II_T Measurement device TTL_IN TTL_OUT IO_T A VI_T V VO_T (a) TTL I/O DC characteristics measurement circuit Measurement device Pulse generator TTL_IN TTL_OUT Probe Oscilloscope CL CL = 10 pF (including the probe capacitance) (b) TTL I/O AC characteristics measurement circuit II_E Measurement device ECL_IN ECL_OUT 50 VCCE - 2V A VI_TE V VO_E (c) ECL I/O DC characteristics measurement circuit VCCE - 2V 50 Pulse generator 50 50 Transmission Line VCCE - 2V VCCE - 2V C 2 pF (input capacitance of the measurement equipment and floating capacitance) Measurement device ECL_IN ECL_IN ECL_OUT ECL_OUT 50 VCCE - 2V 50 Oscilloscope (d) ECL I/O AC characteristics measurement circuit Measurement device 6.640625MHz VCCE - 2V 50 Triger Pulse pattern generator 265.625MBPS SDIN SDIN SOUT SOUT 265.625Mbps 50 VCCE - 2V Oscilloscope (e) Jitter characteristics measurement circuit - 15 - CXB1583Q Notes on Operation 1. Clock synthesizer (PLL) The CXB1583Q has a PLL-based clock synthesizer for generating the serial data transfer frequency (transmission bit clock) and clock recovery circuit for recovering the clock from the reception serial data. These circuits require the external loop filters and external resistors which determine the VCO center frequency. The external part circuit and recommended constant values are shown in the figure below. The parasitic capacitance attached to the pins which are used to connect external parts should be kept as small as possible in order to obtain the good PLL characteristics. 52 R1 53 R2 R5 56 R3 58 59 R4 C1 C1 : 0.01F C2 : 0.01F R1 : 1.8k R2 : 1.8k R3 : 2.0k R4 : 2.0k R5 : 2.2k C2 Fig. 1. External Part Circuit and Recommended Constants - 16 - CXB1583Q 2. ECL input circuit The ECL differential input pins are biased to VBB (VCC - 1.3 V) via an 18k resistor in the IC. See the figures below for ECL differential input methods. VCC = 3.3V VCC = 3.3V, VEE = GND VCC = 3.3V, VEE = GND VBB (VCC - 1.3V) 18k 18k 82 3.3V ECL output buffer 82 ECL differential input buffer (a) ECL differrential signal from 3.3V ECL output buffer VCC = GND, VEE = -4.5V VCC = 3.3V, VEE = GND VBB (VCC - 1.3V) 0.01F 18k 0.01F 330 ECL100K output buffer 330 VEE 18k ECL differential input buffer (b) ECL differrential signal from ECL 100K output buffer VCC = 3.3V, VEE = GND VBB (VCC - 1.3V) 0.01F 50 TRANS. LINE 50 50 VTT (VCC - 2V) ECL differential input buffer 18k 0.01F 18k (c) ECL differrential signal from 50 transmission line VCC = 3.3V, VEE = GND VBB (VCC - 1.3V) 0.01F 50W TRANS. LINE 50 VTT (VCC - 2V) ECL differential input buffer 18k 0.01F 18k (d) ECL single signal from 50 transmission line Fig. 2. ECL Input Circuits - 17 - CXB1583Q 3. Example of power supply circuit VCCT 3.3V 22F 0.1F 22F VCCG VCCE 0.1F VEEG VEEE 22F VCCP 0.1F VEET VEEP Fig. 3. Example of power supply circuit 4. Power-on reset signal (POR) The CXB1583Q has the power-on reset signal (POR). This signal functions as a system reset signal when the power is turned on, the low level of signal is output for approximately 100ns and then the high level results. POR Output Tpor Power On Fig. 4. Power-on reset signal - 18 - CXB1583Q Example of Representative Characteristics Example of Rj measurement (RX recovered clock, 266MHz operation) [ 100mV/div ] TX input (PDI0 to 9): Random data RX input (SDIN): K28.5 Ta = 27C Rj = 26.3ps (RMS) [ 100ps/div ] Example of Rj measurement (RX recovered clock, 200MHz operation) [ 100mV/div ] TX input (PDI0 to 9): Random data RX input (SDIN): K28.5 Ta = 27C Rj = 36.9ps (RMS) [ 100ps/div ] - 19 - CXB1583Q Example of Rj measurement (SDOUT, 266Mbps operation) [ 100mV/div ] TX input (PDI0 to 9): Random data Ta = 27C Rj = 17.6ps (RMS) [ 100ps/div ] Example of Rj measurement (SDOUT 200Mbps operation) [ 100mV/div ] TX input (PDI0 to 9): Random data Ta = 27C Rj = 24.3ps (RMS) [ 100ps/div ] - 20 - CXB1583Q Eye pattern (TX SDOUT, 266Mbps operation) [ 200mV/div ] Ta = 27C [ 1ns/div ] Eye pattern (TX SDOUT, 200Mbps operation) [ 200mV/div ] Ta = 27C [ 1ns/div ] - 21 - CXB1583Q Eye pattern (RX retimed data, 266Mbps operation) [ 200mV/div ] Ta = 27C [ 1ns/div ] Eye pattern (RX retimed data, 200Mbps operation) [ 200mV/div ] Ta = 27C [ 1ns/div ] - 22 - CXB1583Q Package Outline Unit: mm 80PIN QFP (PLASTIC) + 0.35 1.5 - 0.15 + 0.1 0.127 - 0.05 0.1 41 40 16.0 0.4 + 0.4 14.0 - 0.1 60 61 80 1 0.65 20 21 + 0.15 0.1 - 0.1 0.12 M 0 to 10 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-80P-L03 LQFP080-P-1414 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 0.6g - 23 - 0.5 0.2 + 0.15 0.3 - 0.1 (15.0) |
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